The present invention relates generally to electronic circuits. More particularly, it pertains to a structure and methods for low power supply differential amplifiers using a novel complementary metal oxide semiconductor (CMOS) topology.
Decreasing power supply voltages in CMOS technology pose serious challenges in the design of analog integrated circuits and analog functions, e.g. analog differential amplification, when used conjunctively in digital integrated circuits. Power supply voltages in such integrated circuits have decreased from 5.0 V to 3.3 V and 2.5 V, with development work being done on dynamic random access memories (DRAMs) which use power supplies as low as 0.9 V.
The basic problem with using conventional analog differential and/or operational amplifiers in CMOS technology is two-fold. First, high and variable values for threshold voltages (VT) plague the precision of transistor operation using 1 micron (1 xcexc) CMOS technology. This is the same 1 xcexc CMOS technology which is fundamental for low power operation. Second, the circuit configuration of a conventional amplifier is troublesome since the conventional amplifier requires stacking three devices one on top of each other. In its basic form, the three devices of the differential amplifier involve a current sink device, designed to provide common mode feedback and rejection, a pair of transistors for amplification, and a pair of load devices. Operation criteria demand that some significant overdrive, e.g., the excess in a transistor""s gate to source potential (VGS) over the transistor""s threshold voltage (VT), or (VGS-VT), is required in order to provide reasonable gain (G).
In addition to reasonable gain (G), another important performance criteria of the differential amplifier is the unity current gain frequency (fT). The unity current gain frequency, fT, depends on the transconductance (gm) of the amplifying transistor, and similarly depends on the overdrive, VGS-VT. To achieve reasonable values of transconductance and frequency response, VGS again must be significantly larger than VT. Generally, the unity gain frequency (fT) of a transistor is given by:
2xcfx80(fT)=gm/(Cgs+Cgd),
where Cgs is the gate to source capacitance for the transistor, Cgd is the gate to drain capacitance for the transistor, and gm is the transconductance of the transistor. The transconductance, gm, is also generally expressed by:
gm=xcexcC0(W/L)(VGSxe2x88x92VT).
In the conventional differential amplifier configuration the current sink, designed to minimize common mode gain and provide a high common mode rejection ratio, poses one of the significant obstacles to low power operation. The obstacle is that a current sink, designed to minimize common mode gain and provide a high common mode rejection ratio, generally requires a significant voltage drop. As the electronics industry continues it""s push for low power devices, e.g. power supplies of less than 1.0 volt, the conventional differential amplifier in it""s three device circuit stack form simply cannot provide acceptable performance.
Research into the above described problem has provided certain differential nd/or operational amplifier configurations which operate with lower power supply voltages. For instance, Motorola has a patent and publication on a special combination of metal oxide semiconductor (MOS) technology and bipolar technology which produces an operational amplifier capable of operating with power supply voltages as low as 1.2 V. Unfortunately, the combined MOS/bipolar technology construction sacrifices the advantages to manufacturing in a streamlined, solely CMOS, technology process.
Another approach has produced CMOS amplifiers which can function with 1.2 V power supplies, but these operate only at very low frequencies below the megahertz (MHZ) range. Present performance criteria for dynamic random access memories (DRAMs), and other digital circuits which use CMOS amplifiers, requires operation at frequencies approaching the gigahertz (GHz) range. Given that differential amplifiers are normally required in DRAM sense amplifier circuits, then there is a requirement for low voltage differential amplifiers which operate not only in traditional analog integrated circuits but also digital integrated circuits like DRAMs. In this environment, low voltage differential amplifiers must satisfy reasonable gain (G) expectations and have high frequency response characteristics.
The constant reduction in power supply voltages presses the requirement to have differential amplifiers which can function at voltages lower than 1.0 V and still provide a high unity current gain frequency (fT) in the GHz range. Such amplifiers can be used as basic building blocks in analog circuits and for special functions in digital integrated circuits such as sense amplifiers.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, it is desirable to develop improved amplifiers which can be fabricated according to a CMOS process and which can operate at power supply voltages of 1.0 V and below. It is further necessary that such amplifiers supply sizeable gain (G) and have high frequency response characteristics.
The above mentioned problems with differential amplifier configuration and operation as well as other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are provided which accord exemplary performance.
High performance, wide bandwidth or very fast CMOS amplifiers are possible using the new circuit topology of the present invention. The differential amplifier of the present invention employs a novel common mode feedback circuit to back bias the body regions of the amplifying transistors in the differential amplifier. The novel configuration is achieved entirely using CMOS fabrication techniques and delivers high performance in both amplifier gain (G) and frequency response (ft) characteristics using a 1 micron (1 xcexc) CMOS technology.
In one exemplary embodiment, the common mode feedback circuit is fabricated on a different portion of a semiconductor substrate apart from the amplifying transistors and load devices of the differential amplifier. Thus, the present invention avoids stacking, three high, the three principle circuit components of the differential amplifier.
The inventive common mode feedback circuit reduces high and variable values for threshold voltages (VT) which plague the precision of transistor operation using 1 micron (1 xcexc) CMOS technology. The CMOS differential amplifier topology facilitates component transistor operation having low and stable threshold voltages (VT) of less than 0.1 V. In this manner, the CMOS amplifier delivers high performance criteria at very low power supply voltages, e.g., less than 1.0 V. At these low power supply voltages unity voltage gain frequencies in excess of 1 GHz are achieved. Additionally, the CMOS differential amplifier topology of the present invention provides increased gain performance. The low threshold voltage (VT) values and low threshold voltage (VT) variance, facilitated by the novel common mode feedback circuit, yield significant differential gain (ADM) at low power supply voltages. The common mode signal of the present invention is reduced by the gain of the novel common mode feedback circuit (AFB), thus producing a low common mode gain (ACM) and a high common mode rejection ratio.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.